= : Assign

= : Assign

Parameter	Data Type	Memory Area	Description
<address>	BOOL	I, Q, M, D, L	The address specifies the bit to which the signal state of the string of logic operations is assigned.

Description

The Assign instruction produces the result of logic operation. The box at the end of a logic operation has the signal 1 or 0 according to the following criteria:

·       The output has the signal 1 when the conditions of the logic operation before the output box are satisfied.

·       The output has the signal 0 when the conditions of the logic operation before the output box are not satisfied.

The FBD logic operation assigns the signal state to the output that is addressed by the instruction (to achieve the same effect, the signal state of the RLO bit could also be assigned to the address). If the conditions of the FBD logic operations are

satisfied, the signal state at the output box is 1. Otherwise the signal state is 0. The

Assign instruction is influenced by the Master Control Relay (MCR).

For more detailed information about the functions of the MCR, refer to MCR on/off. You can only place the Assign box at the right-hand end of the string of logic

operations. You can, however, use several Assign boxes.

You can create a negated assignment with the Negate Input instruction.

Status Word

	BR	CC 1	CC 0	OV	OS	OR	STA	RLO	FC
writes	-	-	-	-	-	0	X	-	0