4:26 AM
0

Symbol


MCR<






MCR On


The Master Control Relay On (MCR<) instruction triggers an operation that saves the RLO in the MCR stack and opens an MCR zone. The instructions shown in MCR Instructions are influenced by this RLO that is saved in the MCR stack when the MCR zone is opened.

The MCR stack works like a LIFO (Last In, First Out) buffer. Only eight entries are possible. If the stack is already full, the Master Control Relay On instruction produces an MCR stack error (MCRF).




Symbol


MCR>






MCR Off


The Master Control Relay Off (MCR>) instruction closes the MCR zone that was opened last. The instruction does this by removing the RLO entry from the MCR stack. The RLO was saved there by the Master Control Relay On instruction. The entry released at the other end of the LIFO (Last In, First Out) MCR stack is set to
1.

If the stack is already empty, the Master Control Relay Off instruction produces an MCR stack error (MCRF).






MCR-Stack



The MCR is controlled by a stack which is one bit wide and eight entries deep. The MCR is activated as long as all eight entries in the stack are equal to 1. The MCR< instruction copies the RLO to the MCR stack. The MCR> instruction removes the last entry from the stack and sets the released stack address to 1.



If an error occurs, for example, if there are more than eight MCR> instructions in succession, or you attempt to execute the instruction MCR> when the stack is empty, the MCRF error message is activated.

0 comments:

Post a Comment

Labels

Actuator Sensor-interface Address Negative Edge Detection Address Positive Edge Detection ADDRESSING ANALOG INPUTS ANALOG OUTPUTS AND Logic Operation AS-i AS-i configuration Assign Authorizations Automation License Manager BASICS Bit Bit Configuration Bit Logic Instructions Block By-passing CiR CiR Modules CiR Objects communication COMPARISON Components Configuration Configuring Connections Conversion Converting Counter CP 343-2 P CP 443-5 Ext CPU CPU 412-1 CPU 412-2 DP CPU 412-2 PCI CPU 414-2 DP CPU 414-3 DP CPU 414-4 H CPU 416-2 DP CPU 416-2 PCI CPU 416-3 DP CPU 416F-2 CPU 417-4 CPU 417-4 H Data Block DI/DO MODULES Diagnosing Diagnosis DIGITAL INPUTS DIGITAL OUTPUTS Downloading DP master English Mnemonics ET 200M Exclusive OR Logic Operation Extended pulse timer fail-safe modules fault FBD Floating- Point Floating-Point Math FUNCTION MODULES German Mnemonics Hardware hmi Input Insert Binary Input install Instructions Integer Math INTERFACE MODULES Jump License License Keys Load Memory Master Control Relay Memory Areas Memory Reset Midline Output Modifying MODULES monitoring variables Move NEG Negate Binary Input Negative RLO Edge Detection Networks Off-delay timer On-delay timer Operating systems OR Logic Operation Output PID Control PLC POS position decoder Positive RLO Edge Detection PROFIBUS Program Control programm Programming Pulse timer RELAY OUTPUTS Remote Reset Output Reset_Set Flip Flop Retentive on-delay timer Rotate RS S5 File S7 Communications S7-300 S7-400 SAVE Save RLO to BR Memory SCADA Set Output Set_Reset Flip Flop Shift siemens SIMATIC SIMATIC Manager Slaves Software SR STATEMENT Status Bit STEP 7 stop mode Time Base Time Value Timer Timer Cell TRAINING MODULE Units Upgrading UPLOADING WinLC RTX Word Logic Work Memory XOR